Fix live-device slot ID resolution, add print and tighten wire routing

_slot_name_by_id() now resolves SOX link slot IDs against the
inheritance-flattened final_components_registry instead of the
per-type slot_registry whose local IDs were wrong for types with
intermediate parents (e.g. RegFloat→Register→Component). This
produced incorrect link endpoints, inflated linked-slot visibility,
and different box sizes between file and live modes.

Also: tighten routing constants for denser wiring, add wiresheet
PNG print/export (Ctrl+P), sort link routing jobs by gap distance,
remove debug route logging, and fix live tree-expand re-selection.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

device_session.py

@@ -339,6 +339,17 @@ class DeviceSession:
                                      "to": f"{to_path}.{to_slot_name}"})
 
     def _slot_name_by_id(self, kit_id, type_id_val, slot_id):
+        # SOX links use absolute slot IDs across the full inheritance chain.
+        # final_components_registry has correctly resolved absolute IDs;
+        # the per-type slot_registry only stores local (per-type) IDs
+        # which are wrong for types with intermediate parents.
+        type_name = self.sox_client.type_name_map.get((kit_id, type_id_val))
+        if type_name and type_name in app_state.final_components_registry:
+            for s in app_state.final_components_registry[type_name]:
+                if s["slot_id"] == slot_id:
+                    return s["name"]
+        # Fallback to slot_registry (local IDs — wrong for inherited types,
+        # but keeps things working when the schema registry is not yet loaded)
         slots = self.sox_client.slot_registry.get((kit_id, type_id_val))
         if slots:
             for s in slots: