Fix live wiresheet: resolve type names and load schema gracefully

- Add type_name_map on SoxClient so components loaded after connect
  resolve proper names (e.g. control::And2) instead of kit::typeN.
  This lets the slot registry and final_components_registry match,
  so component boxes show their slots and property values.

- Load live schema gracefully: skip missing kit manifests instead of
  aborting, compile the kits we have, and warn about missing ones in
  the status bar.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

sox.py

@@ -363,6 +363,10 @@ class SoxClient:
         # each slot dict: {name, id, type_name, is_config, is_runtime, is_action, is_operator, is_as_str}
         self.slot_registry = {}
 
+        # type name map — set externally by device_session
+        # maps (kit_id, type_id) -> "kit::TypeName" for proper type resolution
+        self.type_name_map = {}
+
         # event callback: called on main thread via queue
         self.on_event = None        # fn(comp_id, what_char)
 
@@ -853,6 +857,9 @@ class SoxClient:
         comp.links = links
 
     def _resolve_type_name(self, kit_id, type_id_val):
+        resolved = self.type_name_map.get((kit_id, type_id_val))
+        if resolved:
+            return resolved
         if self.schema_parts and 0 <= kit_id < len(self.schema_parts):
             kit_name = self.schema_parts[kit_id].name
         else: