Fix live wiresheet: resolve type names and load schema gracefully

- Add type_name_map on SoxClient so components loaded after connect
  resolve proper names (e.g. control::And2) instead of kit::typeN.
  This lets the slot registry and final_components_registry match,
  so component boxes show their slots and property values.

- Load live schema gracefully: skip missing kit manifests instead of
  aborting, compile the kits we have, and warn about missing ones in
  the status bar.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

device_session.py

@@ -142,6 +142,7 @@ class DeviceSession:
                 })
             registry[(kit_id, type_id_val)] = slots
             full_name = f"{kit_name}::{type_name}"
+            self.sox_client.type_name_map[(kit_id, type_id_val)] = full_name
             # update type_name on any cached component of this type
             for c in self.sox_client.cache:
                 if c is not None and c.kit_id == kit_id and c.type_id == type_id_val: