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Fix live wiresheet: resolve type names and load schema gracefully

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- Add type_name_map on SoxClient so components loaded after connect
  resolve proper names (e.g. control::And2) instead of kit::typeN.
  This lets the slot registry and final_components_registry match,
  so component boxes show their slots and property values.

- Load live schema gracefully: skip missing kit manifests instead of
  aborting, compile the kits we have, and warn about missing ones in
  the status bar.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Arda
2026-09-12 13:43:44 +03:00
co-authored by Claude Opus 4.6
parent 4c90c1c241
commit 4e38847f91
4 changed files with 32 additions and 8 deletions
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app_state.py
+1 -1
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@@ -8,7 +8,7 @@ so later rebinding would only ever be seen by the module that did it.
import configparser
import os
VERSION = "0.0.0.084"
VERSION = "0.0.0.085"
PROPERTIES_FILE = os.path.join(os.path.dirname(os.path.abspath(__file__)), "editor.properties")
DEFAULT_GRID_SIZE = 10
DEFAULT_ADD_TIMESTAMP = True